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| Mini IOM-2 Controller MICO PEF 2015 Version 1.1 Addendum 03.98 to the Data Sheet 12.97 Bus Interface Timing For proper operation of the MICO the timings in figures 19a and 20 (Data Sheet 12.97) are depicted more detailed concerning the RD, WR, CS signals (Siemens/Intel mode) and the R/W, DS signals (Motorola mode), respectively. Between two read (write) accesses in Intel mode the according control signal RD (WR) has to be deactivated. Thus a read/write cycle control by only asserting and deasserting CS is not possible. The same applies to the DS signal in Motorola mode. Bus Interface Timing Parameter R or W set-up to DS R or W hold time from DS RD-pulse width RD-control interval Symbol Limit Values min. max. ns 10 80 40 80 25 45 40 0 15 ns ns ns ns ns ns ns ns ns 0 Unit tDSD tRWh tRR tRI Data output delay from RDxCS,DSxCS tRD Data float delay from RDxCS, DSxCS tDF tWW WR-pulse width tWI WR-control interval tDW Data set-up time to WRxCS, DSxCS tWD Data hold time from WRxCS, DSxCS Siemens Semiconductor Group (c) Siemens AG 1998. All Rights Reserved. DS 1 Please note that any information contained in this publication may be subject to change. Siemens reserves the right to make changes to or to discontinue any product or service identified in this publication without notice. Please contact our regional offices to receive the latest version of the relevant information to verify, before placing orders, that the information being relied upon is current. Revision History: Previous Version: Major Changes: PEF 2015 uP Read Cycle tRI RD tRR CS x RD tRD D0D7 tDF 'DWD 7PRG Figure 1 Siemens/Intel Bus Mode Semiconductor Group 2 03.98 PEF 2015 P Read Cycle tRI DS R /W tDSD tRR tRWh CS x DS tRD tDF Data 7PRG D0 - D7 P Write Cycle tWI DS R/W tDSD tWW tRWh CS x DS tDW tWD D0 - D7 Data 7PRG Figure 2 Motorola Mode Semiconductor Group 3 03.98 |
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